T-VEC develops some of the world’s most advanced model-based verification and testing tools. In development for over 15 years, these tools automate error analysis and test generation for both requirements and design models.
They detect problems early when they are least expensive to correct and prevent them from impacting downstream development activities. During verification they automate the typically labor-intensive and error-prone test design process to produce more effective and comprehensive tests.
Lower development costs
Faster development cycles
Objective measures of performance
Reduced cost and rework
Better tests find hidden bugs
Reduced manual efforts through test driver generation
The T-VEC tool suite is composed of three applications:
1) T-VEC Tabular Modeler (TTM)
2) T-VEC Tester for Simulink®
3) T-VEC Vector Generation System (VGS)
TTM provides an easy to use graphical interface for creating precise and consistent requirements and using these as a basis for: requirement management, automated requirements defect detection, automated test case creation and execution, and requirements-to-test traceability. TTM integrates also with Telelogic® DOORS®.
The T-VEC Tester for Simulink® and Stateflow® performs model checking, test vector generation, test driver and harness generation for The Mathworks Real Time Works® and MATLAB® simulator, test results analysis, and report generation. The T-VEC Tester provides fully automated execution through a GUI integrated within MATLAB®, or through command interface for batch processing.
T-VEC VGS is the core engine used by both TTM and the T-VEC Tester to support model analysis, proving system properties, test vector generation, and test drivers for virtually any language supporting test execution in simulation, host, or target test environments, with comprehensive report generation supporting fully hyperlinked documentation, model error analysis, status, and metrics. For more details see www.t-vec.com
The T-VEC product family has been proven to scale to large systems while fully integrating requirement modeling, model checking, and test generation tools with requirement management, design modeling, and test code coverage tools to provide full life cycle support and tool integration (e.g., DOORS® to LDRA Tbrun®). T-VEC test vector generator systematically selects test values at the boundaries (linear and non-linear equalities/inequalities, discrete and floating point computations) associated with the constraints for every thread of a system to provide the most effective test points for exposing defects, while exceeding the MC/DC test coverage criteria required to comply with DO-178B.
In addition, the T-VEC tools provide test vector sequence generation to support verification of dynamic systems with feedback, model checking for both requirement and design models to assist with model validation, and a customizable test driver generation facility allowing generated tests to be targeted to virtually any environment.
Also visit :www.t-vec.com